The present invention relates in general to semiconductor devices and in particular to various embodiments of semiconductor structures formed on various substrates such as metal and methods of manufacturing such devices.
Generally, conventional semiconductor manufacturing utilizes a number of processes to form semiconductor structures on substrates. The substrate is typically part of a wafer. A wafer is a small thin circular slice of a semiconducting material, such as silicon, on which semiconductor structures are formed. Standard device fabrication processes, such as etching, deposition, and plating are used to fabricate semiconductor structures on the wafer. After the formation of the semiconductor structures, the wafer is tested and then diced up to separate individual semiconductor structures, generally called dies, which include a substrate layer. A substrate layer (substrate) is often referred to as the base layer or body of the die onto which other layers are deposited to form the semiconductor structures. Semiconductor structures formed on the substrate may be discrete devices or integrated circuits. For example, the semiconductor structure may be composed of a single discrete power transistor, or may be formed from a number of transistors and other electronic elements, such as resistors, capacitors, etc., that are electrically coupled together to form an integrated circuit.
The substrate plays a critical role with the semiconductor structures it supports whether it is a discrete device, such as a power transistor, or an integrated circuit. The substrate is often used to structurally support the semiconductor structure from damage due to mechanical flexing. The substrate may also be used as part of the semiconductor structure, supporting vertical or lateral current flows. In some devices, the substrate is used as an insulator where the substrate is configured to insulate the semiconductor structure from other semiconductor structures or from electronically coupling to a conductive surface.
Depending on its properties and dimensions, a substrate may adversely impact the performance of semiconductor structures it supports. The substrate may introduce unwanted parasitic impedances and heat conduction paths that can affect the power consumption, the power dissipation, and the operational bandwidth of a semiconductor structure. For example, in the case of a typical complementary metal oxide semiconductor (CMOS) integrated circuit, the substrate may contribute to latch-up. Placing the CMOS devices on an insulating substrate e.g., silicon-on-insulator (SOI) instead of a conducting substrate can reduce current leakage and help prevent latch-up, however, the insulating substrate also may limit the heat conduction from the CMOS circuitry. For radio frequency (RF) devices, the substrate is often a critical design element with respect to transmission lines used to transmit high speed data. The thickness and type of substrate material is important to the transmission efficiency of such high speed signals. The substrate often plays a key role in the heat dissipation of the semiconductor structure. For example, a metal substrate may be used to help draw heat from a device to an external environment. Therefore, the thickness, material, and structural design of the substrate layer are critical components of the performance and structural integrity of the semiconductor structure it supports.
In certain devices, the substrate is used as part of the current conduction path. For example, the substrate plays an important role with the solid state switch which is a key semiconductor structure used for discrete device applications and integrated circuits. Solid state switches include, for example, the power metal-oxide-semiconductor field effect transistor (power MOSFET), the insulated-gate bipolar transistor (IGBT) and various types of thyristors. Some of the defining performance characteristics for the power switch are its on-resistance (i.e., drain-to-source on-resistance, RDSon), breakdown voltage, and switching speed. Depending on the requirements of a particular application, a different emphasis is placed on each of these performance criteria. For example, for power applications greater than about 300-400 volts, the IGBT exhibits an inherently lower on-resistance as compared to the power MOSFET, but its switching speed is lower due to its slower turn off characteristics. Therefore, for applications greater than 400 volts with low switching frequencies requiring low on-resistance, the IGBT is the preferred switch while the power MOSFET is often the device of choice for relatively higher frequency applications.
Generally, the switching speed, on-resistance, breakdown voltage, and power dissipation of a typical MOSFET device is influenced by the layout, dimensions, and materials. Industry design practice has sought to keep the on-resistance of the MOSFET as low as possible to lower static power loss and increase current densities. For example, in vertical power MOSFET devices, the on-resistance is composed of several resistances such as channel resistance, epitaxial layer resistance, and substrate resistance. The on-resistance of such a vertical power MOSFET device (as well as other MOSFET devices) is directly influenced by the type and dimensions of materials used to form the drain to source conduction path. Therefore, for a vertical power MOSFET, the substrate is a critical performance element.
In addition to the substrate layer, the semiconductor layers forming semiconductor structures such as MOSFETs and CMOS circuitry inherently impart an influence on the operational performance of the semiconductor structures. The substrate layer and semiconductor layers introduce parasitic effects, that are inherent in the substrate and semiconductor layers, to the semiconductor structures. For example, parasitic capacitances and inductances are directly affected by the materials used for the semiconductor layers and substrate (e.g., insulator, semiconductor, doping concentration, etc.) and the dimensions (e.g., height, width, length, etc.) used to form and support the semiconductor structures. Such parasitic effects generally lead to a degradation of the semiconductor structure electrical performance and operation.
Generally, smaller dimensions in semiconductor structures tend to reduce parameters such as resistance, power dissipation, and parasitic impedance. With regard to the semiconductor layers, for example, the thinner the semiconductor layers the better the semiconductor structure frequency of operation. Also, larger specific heat capacitance and more heat capacitive substrate materials tend to increase the heat dissipation ability of the semiconductor structures, whereas thinner substrates tend to improve frequency of operation for those devices that rely on the substrate as part of the conduction path. However, as semiconductor structures decrease in size, providing thinner semiconductor layers and substrates presents process challenges for semiconductor manufacturers. In conventional semiconductor structure fabrication processes, after semiconductor structures, other semiconductor layers, and metal layers have been applied to the substrate, the substrate is often thinned using a process such as chemical mechanical polishing (CMP). Chemical etching processes have been developed to further etch the substrate to a thinner profile, but chemical etching process are difficult to control and often lead to damaged semiconductor structures that are inadvertently etched during the process. In addition, conventional substrate thinning processes have inherit limitations as the semiconductor structures require some structural support. Therefore, conventional processes to thin the substrate generally produce some defective semiconductor structures due to etching errors and the mechanical flexing of the substrate.
There is therefore a need for structures and methods to form semiconductor structures with optimized semiconductor layers and substrates to improve operational performance while minimizing process related defects due to structural stresses.